91.305 MIDTERM NOTES SPRING 2004 ******** BRING ALL DATA SHEETS! ********* YOU WILL NEED THE HC11 DATA SHEET AND THE 74HCxx DATA SHEETS 1 PAGE OF PERSONALLY PREPARED NOTES (BOTH SIDES) MAY ALSO BE BROUGHT. THESE ARE TO BE TURNED IN WITH EXAM (YOU WILL GET BACK). Here is a list of topics you should be familiar with, Including activities that you might be asked to perform based on these topics. ---------------------------------------------------------------------- Circuits and Transistors V= IR (calculating voltage, current, and resistance given 2 of 3) NPN transistor circuits (models of current flow, BE current x beta (gain) yields CE current) electrical properties of digital logic (input current, output current, valid voltages, being able to read this from data sheets, source vs. sink) ---------------------------------------------------------------------- Logic universality of NAND and NOR (being able to build other gates from either of these two) DeMorgan's Laws (various forms of same idea) typical logical elements (what they are, what you can do with them): and/or/xor/not/ etc basic gates S-R latches (built with NOR) flip-flops (JK and D, edge triggered) decoders (e.g., HC138) counters (e.g., HC393) registers (e.g., HC574) ---------------------------------------------------------------------- State Machines understanding and creating state transition diagram assignment of unique #s to different states indicating transition conditions creating state transition table from diagram creating logic equations from table minimizing equations implementing equations with gates and HC574 latch ---------------------------------------------------------------------- Frequency and Period 1 ns (nanosecond, 10^-9 sec) -> 1 GHz (gigahertz, 10^9 cycles/sec or Hz) 1 us (microsec, 10^-6 sec) -> 1 MHz (megahertz, 10^6 Hz) 1 ms (millisec, 10^-3 sec) -> 1 kHz (kilohertz, 10^3 Hz) ---------------------------------------------------------------------- HC11 register model (set of internal registers) memory map of HC11 16 addr bits -> 65535 aka 64K of addr space 0x0000-0x01ff is RAM 0x1000-103F is ctrl register bank control registers how to interact with them (e.g., ldaa PORTA; eora 0x10; staa PORTA) the addressing modes (inherent, immediate, direct [zero page, 1 byte], extended [whole 64k range, 2 bytes] , indexed-X and -Y) hand-assembling single instructions into a sequence of 1 or more bytes e.g., with use of HC11 data sheet, convert "LDAA #48" into byte-sequence "0x86 0x30" status register/condition codes which instructions set them how branches use them (e.g., "bne xxx" takes branch if Z bit is 0) subroutines/use of stack stack builds downward in memory (from high addr toward low addr) jsr or bsr causes push of return address (2 bytes) low byte is pushed first, high byte second single-chip mode vs. expanded-mode (e.g., in expanded mode, Port C is the multiplexed address/data bus) memory mapping latches and RAM (e.g., looking at a schematic and figuring out where in memory a device is located.)