FALL 2004 MIDTERM PREP NOTES

1 The midterm is Fri Oct 22 2004.
2 Any/all of the following topics may be tested on the midterm.
3 Open book/open notes/calculator allowed.
4 Make sure to bring yellow HC11 reference manual!  You *will* need it.
5 Use the ikonboard to discuss any issues betw now and then.


BIT STUFF
* operation and signficance of N, Z, C bits
* corresponding branch ops: beq, bne, bcs, bcc, bpl, bmi 
* bitmasking:  using OR to set bits and AND to clear bits;
  determining correct mask and operation given desire to set or clear a
  named bit or bits
* using XOR to flip bits


FREQ CALC
* being able to cvt from s, ms, usec
* half-period vs. period (being able to calc freq based on either)
* converting periods to freq/ freq to period
* cvt period to # of E clocks / E clocks to period
* analyzing code to count E clocks


HC11 CODE AND ADDR MODES
* analyzing/understanding the operation of provided HC11 programs
* assembly/disassembly (converting betw binary opcodes and mnemonics)
* immediate mode (load a number into the register) using # symbol
* direct/extended mode (provide fixed ptr in the instruction)
* indexed X/Y mode (X or Y reg value + a 1-byte offset as ptr)
* inherent (no memory access)
* stack (SP register used as ptr)


NUMBER SYSTEMS:
* understanding wrapping w/8- and 16-bit numbers (e.g., if hc11
register A =0, after deca it's 255; if HC11 register X=0, after DEX
it's 0xFFFF)
* converting betw signed integers and 2's complement representations
-- 8 bit registers hold unsigned 0 to 255 or signed -128 to +127;
   0x01 == +1 (2s compl) == 1 (unsigned)
   0x80 == -128 (2s compl) == 128 (unsigned)
   0xFF == -1 (2s compl) == 255 (unsigned)
-- 16 bit regs hold unsigned 0 to 65535 or signed -32768 to +32767;
   0x0001 == +1 (2s compl) == 1 (unsigned)
   0x7fff == +32767 (2s compl) == 32767 (unsigned)
   0x8000 == -32768 (2s compl) == 32768 (unsigned)
   0xFFFF == -1 (2s compl) == 65535 (unsigned)
-- algorithm for cvt'ing 2s compl bit patterns to signed values (page
10 of 6811intr.pdf document) 


HC11 STACK AND MEMORY:
-- big-endian (big end/most-significant-byte FIRST or in earlier/lower
memory addresses)
-- stack grows "downward" (toward lower memory addrs)
-- when pushing 16-bit vals, low byte is pushed first/high byte
second, so that when in memory, it's big-endian
-- jsr (jump to subroutine) and bsr (branch to subroutine) both push
16-bit ret'n addr (i.e., the addr of the very next instr in memory)
onto stack
-- stack pulls (pops) don't destroy memory, just read out of stack and
adjust the stack ptr


ADDRESS DECODING:
* be able to determine what behavior of diff HC138 ckts is
* be able to design/analyze a ckt with an HC138
* how many bits for memories of diff sizes (up to 64k); e.g., 8k
memory requires 13 addr bits (2^13 = 8192, or 2^16=64k and 2^3=8, so
[dividing] 2^13 = 8k)
* how to map a memory to diff areas of hc11 addr space (by decoding
high order hc11 addr bits to a particular value, and wiring low order
bits to the addr bits of the RAM)
* what happens if bits are left un-decoded (accessing diff addrs will
result in the same operation; e.g., if only upper 4 bits are decoded,
then any of 4k diff addr accesses will result in the same select line
being enabled)
* HC11 R/~W line (1 for read, 0 for write)
* E clock (low/0 phase is addr set-up; high/1 phase is "do it";
latches and memories must include E=1 in decode/enable logic)