91.305 COMPUTER ARCHITECTURE
Fall 2004 

Final study guide

* Final is open book/open notes/calculators allowed.
* You will not need data sheets.  The exam will have relevant
  appendices that may be referenced.
* BRING YOUR KIT! (if you haven't returned it already)


Stuff that will NOT be on the final
----------------------------------------
* 68HC11 assembly programming
* reduction of logic equations

Stuff that is EXTREMELY LIKELY to be on the final
(many of these topics will be tested)
-----------------------------------------------------
* understanding and being able to answer questions about x86 assembly
code that was generated by having gcc compile C functions; e.g.:
  - use of %ebp (base ptr/frame ptr) register to access
  function arguments
  - arrays and use of a register as the array index
  - writing C code given x86 asm code

* Y86 processors (SEQ and PIPE):
  - familiarity and understanding of the 4 representations of these
  machines (ISA/asm code, instruction execution tables,
  architectural/schematic drawings, HCL code)
  - ability to indicate where a feature of one of these
  representations is present in another (e.g., given a line of HCL
  code, where in the arch diagram is this code implemented?)

* architecture and functioning of the SEQ machine; e.g.:
  - describing operation of the 6 execution stages (fetch, decode,
  execute, memory, writeback, next-pc)
  - creating a table that explains what is happening at each stage for
  a given existing instruction (or a new one)
  - based on such a table, writing and/or modifying existing HCL code
  to implement a SEQ instruction

* architecture and functioning of the PIPE machine; e.g.,:
  - how data hazards are circumvented using register forwarding
  (pp. 339) 

* principles of modern microprocessor design, including understanding
the relationships amongst the following topics:
  - tradeoffs between a long and short pipeline
  - data hazards and control hazards
  - branch prediction
  - CPI vs. IPC 
  - how superscalar performance is achieved

(You should understand the relationships and design tradeoffs among
all the terms on page 1 of the PC Processor Microarchitecture document
that are bold-faced.  Many of them will be on the exam.)

* cache memory
  - given 3 of the 4 of: (a) cache memory size, (b) block size, (c)
  number of blocks, and (d) number of sets, be able to calculate the
  missing parameter (e.g., practice problem 6.6 [pp. 490])
  - understand the purpose and be able to indicate the tag, set, and
  block bits (given full address space and parameters of the cache)
  (see aside at bottom of pp. 506)
  - be able to simulate the operation of direct-mapped and two-way
  set-associative caches (pp. 492-494)
  - block replacement strategies:  least-recently used,
  least-frequently used
  - write-through/no-write-allocate vs. write-back/write-allocate
  tradeoff 
  - temporal locality, spatial locality, and stride

* how code optimizations affect performance:
  - algorithm design (avoid exponentially-expanding algorithms if possible)
  - loop unrolling
  - code blocking
  - avoiding register spilling
  - writing C code that achieves these