Wed Dec  3 09:22:08 2003
* ass'n 8 back
* kit return fri
* course eval 
* ass'n 10 due fri
* advanced topics in cpu design lecture
already did:
5-stage cpu (fetch, decode, execute, memory, writeback)
pipelined version of same
hazards (data hazards, control hazards)
register forwarding (back into pipeline)
stalls/bubbles
branch prediction (& recovery from mis-prediction)

today:
cpi/ipc (superscalar)
instruction control unit (icu), execution unit
speculative execution
primitive ops (where CISC matched RISC)
functional units
register renaming
retirement unit
out-of-order execution (CDC machine, PPC601, marketing?)
other:
Pentium 4 HT (hyper threading)