Prof. R. J. Lechner

Fall 1996, 91.522 Object-Oriented

Analysis and Design

Owen McGonagle

Computer Science Department

University of Massachusetts at Lowell

December 2, 1996

CHGEN is a code generating tool that supports a data model-based

approach to programming. Object Life Cycle (OLC) Architecture

uses CHGEN generated code to simulate object life cycles in a state

machine operating model. An OLC debugger (OLCDBG) has been

developed to support the stepping through of object life cycles

during state machine execution.

This project uses CHGEN, OLC, and OLCDBG to simulate a

divide-by-8 counter as described in the 91.522 Midterm Exam

given on Tues. March 7, 1995.

Project directories:

$CASE/96f522/omcgonag/JPsim

$CASE/96f522/omcgonag/chgen

Successor project directories:

CHGEN Version 10: $CASE/95s523/genv10/base

OLC Architecture: (CVS Master Repository)

$CASE/95s522/95solc/base/Master/JPsim

Successor project documents:

CHGEN Version 10: $CASE/95s523/genv10/base/doc

OLC Architecture: $CASE/93su523/olc/base/doc

($case/96f522/omcgonag/doc/final.doc)

WP: Microsoft Word 6.0

FINAL REPORT OUTLINE

1. Introduction

1.1 Goals

2. Logic Simulation

3. State Machine

3.1 State Model Creation

3.2 Action Routines

3.3 Event Trace Diagram

4. OLC Debugger (OLCDBG)

5. Building the application

6. Concluding Remarks

Appendix A: Schema file: olc96fa.sch

Appendix B: Header file: olc96fa.h

Appendix C: Network Datafile: run1.dat

Appendix D: Toggle FlipFlop object create: TFFCreate (tfcreate.c)

Appendix E: Toggle FlipFlop Action: TFAction (tfaction.c)

PROJECT STAGES

1. Port of CHGEN and OLC to PC using Borland C/C++:

- Directory build structure

- File name changes

- PC function pointer

- PC 64kb text and data size restrictions.

2. Test of Reinig OLC Architecture two state machine.

3. Development of OLC Debugger.

4. Simulation of process synchronizer

5. Simulation of divide-by-8 counter

6. Build and execute simulation on node jupiter:

- Start from JPsim Master repository.

1. Port Operator class and JPsim to PC.

2. Document all port modifications:

- Bug fixes

- Bugs outstanding