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• lab 6 html

mtg 5: VDK (visual dsp++ kernel)
• lab 5 html
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mtg 4: laser cutter
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mtg 3: FPGA design/implementation
• lab 3 html
• control eng 1800-1930, pp. 96–152 no link
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  – promo pdf
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  – data sheet pdf
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mtg 2: sensors/motors/arch/control
• lab 2 html
• control eng 1800-1930, pp. 51–95 no link
• dynamic pwr mgm't, from BF537 data home page html • sensors html

mtg 1: intro
• syllabus html
• BF-HB manual & schems no link
• BF537 manual (pages 1-13) pdf
• DSP guide zip
• control eng 1800-1930, pp. 1-50 no link
• lab 1 html files

91.548 Lab 3: FPGA Design and Implementation

due February 15


Items with a bullet (•) require something to be turned in.

Reading/Writing Assignment

  1. Read pages 96 – 152 (chapter 4 – “The development of servomechanisms”) of S. Bennett's A history of control engineering, 1800–1930.

Implementation Project

  1. Go through the Xilinx quick start and:
    • create the 4-bit counter.
    • simulate its operation.
    • add it as a schematic symbol to your project.
    • create user constraints that map the:
      • counter's clock and direction inputs to buttons on the Handy Board
      • counter's 4 output bits to LEDs
    • compile the design (“Implement Design”).
    • generate programming file.
    • burn into the HB's SPI flash.

    Power-cycle your Handy Board, and you should now have a 4-bit counter that is clocked from a pushbutton! And the other pushbutton controls up/down!

  2. Implement debouncing on the clock input, so that one button press makes exactly one increment or decrement.

  3. Do one of the following:

    • Use the external 25 MHz oscillator that the HB provides to the FPGA, and daisy-chain some 4-bit counters (or deploy a larger one) to divide the frequency down to something in the kHz range.
    • Figure out how to use the Spartan 3E's built-in Digital Clock Manager to do the same.

    Put the output onto a digital out or servo out pin, and view it on the scope.

  4. Now, do something cool with the FPGA. Possibilities include (but are in no way limited to!):
    • Interface to a sonar sensor, by triggering it and measuring the delay until the return signal.
    • Generate and/or receive modulated IR remote signals.
    • Generate a Cricket Bus signal and talk to Cricket Bus Devices.
    • Talk to the A/D chips directly (code can be provided) and do some signal processing on the conversion stream.
    • Implement PID control in hardware (this is probably hard)
    • Other ideas???

    Many of these projects will require being able to read or write data between the Blackfin and the FPGA. We will provide a solution for this (based on Andrew's earlier work with slightly different design tools).

    Ultimately, we want all of Andrew's existing FPGA code ported to the (free, but not open source) Xilinx toolchain. Presently, much of it uses expensive 3rd party tools (Synplicity's Synplify and Aldec's Active HDL).

    We'll convert or let you convert pieces as needed.

Write up and turn in your work.

Last modified: Wednesday, 15-Feb-2006 16:44:59 EST by fr...@...uml.edu