91.305 FINALS REVIEW
FALL 2003

OPEN-BOOK / OPEN-NOTES EXAM / OPEN TOOLS (CALCULATOR, LAPTOP)


* I'm not retesting from the midterm

	- basic logic & universality of NAND/NOR
	- transistor circuits
	- state machines & logic minimization
	- bit-masking

* other stuff that I won't retest
	- 6811 programming
	- low level timing

exceptions

	- ms, us, ns vs. kHz, MHz, GHz
	- stack

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6. Address decoding  (ass'n 6)
	- address bus and data bus
	- design and interpret address decoding / memory mapping
circuits
	* design a circuit to decode a particular address, or
	* tell me what address a circuit i give you would decode

	- focus on understanding the latch circuit

7. SEQ machine / HCL code to implement it (ass'n 7)

	- write/modify/extend HCL code to implement instructions on
the SEQ architecture

	* transform from HCL code expressions to logic gates (book 4.2)

	* tracing the executing of an instruction by filling in the
Fetch, Decode, Execute, Memory, Write-Back, & PC-Update table

	* implement a new instruction on the architecture by doing the
above
	* understand how the stock instructions move through the
machine, and demonstrate understanding by doing the above

	* be able to write/modify/extend the HCL code for any piece of
the machine (e.g., ALU, register file, PC increment modules)

8.  CPU Research project

	* be able to demonstrate understanding of data sheets by
finding information such as:
	-- how many bits wide is the data bus
	-- how many bits wide is the address bus
	-- what is the CPU clock rate
	-- is it a Harvard or von Neumann architecture? (Harvard has
separate memories for instruction/code stream and data (RAM), v.N. has
unified memory)
	-- how deep is the pipeline, and what are the core stages
	-- what functional units can run in parallel (e.g.,
integer-adders, FP, vector unit, memory-fetch, memory-write)
	-- other things
	-- difference between latency (how long it takes a single
instruction to get thru the machine)  and throughput (how many
instructions per second or cycle)
	-- IPC vs CPI (instr per cyc vs. cyc per instr) and how to
implement each (what are the key archit. features of each) IPC implies
superscalar (has more than one execution unit)

	* i hand you a data sheet and ask you questions about it.

9. PIPE implementation, branch prediction, Y86 code "improvements"
	- branch prediction, choosing & implementing a branch
prediction strategy (always, never, btfnt), how code exercises branch
prediction, misprediction penalty 
	- understand 'register forwarding' --> how to feed results
that will be written to a register back into the pipeline where
they're needed
	- load/use hazards --> pipeline must stall to wait for a value
to be fetched from memory
	- 

10.  Cache memory

	* demonstrate understanding of two primary combinations of
caching strategies (write-back/write-allocate and
write-thru/write-no-allocate) by simulating reads and writes of main
memory thru a cache

	* understand specifications of cache (# of set-bits, # of
block-bits, # of tag bits, etc -- problem 6.21 in the book) and be
able to fill in missing parameters when others are provided.

	* being able to simulate direct-mapped and set-assoc. cache
performance

	* understanding how the dirty-bit works (if you just read a
byte, the cache line came in, but it's clean, so when it's evicted, it
doesn't have to get written to memory)

	* why are L1 and L2 caches used?  

11.  bomb-lab

	* be able to read and interpret basic x86 code

	* demonstrate understanding of how the stack is used for
procedure calls, by:  intepreting code that fetches arguments off the
stack, interpreting code that saves and restores the frame pointer,
interpreting code that creates space for locals (and uses that space
to initialize and work with locals), interpreting code that produces a
function's return value.

	* be able to recognize certain C-language features as they are
implemented in assembly (multiple arguments to a function, simple
loops with an integer counter, if-then statement, array indexing).