***************************************************************************** * These files contain routines that allow the Handyboard to use the Miniboard * as a slave to run a number of sensors and effectors. If you are interested * in some functions we developed, see the (non-BareBones) spi_com.asm, and * bspi.asm files. These routines were written by Dirk Edmonds, John Fischer, * Paul Rybski and Brian Schmalz (in order of the alphabet). * * To connect the Handyboard to the Miniboard you must solder an eight pin * connector to one end of a regulation telephone cable. Assuming the * telephone cable is wired (looking into the connector with the tab on top) * left to right: * (b)lue - (y)ellow - (g)reen - (r)ed - bl(a)ck - white (not connected) * * Then the connector to the spi port on the Handyboard is wired: * _____ * | |by| * |r | | * |g |a | * | | | * ----- * * An extra wire from the Handyboard digital input pin 15 to the Miniboard TxD * is required as a busy flag. * ***************************************************************************** * This is the bare bones version of the communication protocol written * for the Miniboard to be slave to the Handyboard. The only thing here * it a readReg routine (case_0). * * This file should be assembled and loaded onto the Miniboard; spi_comBB.asm * should be assembled and loaded onto the Handyboard. initSpi.c can be loaded * and then INIT_SPI() can be called to get the Handyboard ready to * communicate. ***************************************************************************** * This file should be assembled and loaded onto the Miniboard; spi_comBB.asm * should be assembled and loaded onto the Handyboard. initSpi.c can be loaded * and then INIT_SPI() can be called to get the HB ready to communicate. ***************************************************************************** EEPROM EQU $F800 ; start of eeprom * Control Registers BASE EQU $1000 PORTA EQU $1000 ; Port A data register RESV1 EQU $1001 ; Reserved PIOC EQU $1002 ; Parallel I/O Control register PORTC EQU $1003 ; Port C latched data register PORTB EQU $1004 ; Port B data register PORTCL EQU $1005 ; DDRC EQU $1007 ; Data Direction register for port C PORTD EQU $1008 ; Port D data register DDRD EQU $1009 ; Data Direction register for port D PORTE EQU $100A ; Port E data register CFORC EQU $100B ; Timer Compare Force Register OC1M EQU $100C ; Output Compare 1 Mask register OC1D EQU $100D ; Output Compare 1 Data register * Two-Byte Registers (High,Low -- Use Load & Store Double to access) TCNT EQU $100E ; Timer Count Register TIC1 EQU $1010 ; Timer Input Capture register 1 TIC2 EQU $1012 ; Timer Input Capture register 2 TIC3 EQU $1014 ; Timer Input Capture register 3 TOC1 EQU $1016 ; Timer Output Compare register 1 TOC2 EQU $1018 ; Timer Output Compare register 2 TOC3 EQU $101A ; Timer Output Compare register 3 TOC4 EQU $101C ; Timer Output Compare register 4 TI4O5 EQU $101E ; Timer Input compare 4 or Output compare 5 register TCTL1 EQU $1020 ; Timer Control register 1 TCTL2 EQU $1021 ; Timer Control register 2 TMSK1 EQU $1022 ; main Timer interrupt Mask register 1 TFLG1 EQU $1023 ; main Timer interrupt Flag register 1 TMSK2 EQU $1024 ; misc Timer interrupt Mask register 2 TFLG2 EQU $1025 ; misc Timer interrupt Flag register 2 PACTL EQU $1026 ; Pulse Accumulator Control register PACNT EQU $1027 ; Pulse Accumulator Count register SPCR EQU $1028 ; SPI Control Register SPSR EQU $1029 ; SPI Status Register SPDR EQU $102A ; SPI Data Register BAUD EQU $102B ; SCI Baud Rate Control Register SCCR1 EQU $102C ; SCI Control Register 1 SCCR2 EQU $102D ; SCI Control Register 2 SCSR EQU $102E ; SCI Status Register SCDR EQU $102F ; SCI Data Register ADCTL EQU $1030 ; A/D Control/status Register ADR1 EQU $1031 ; A/D Result Register 1 ADR2 EQU $1032 ; A/D Result Register 2 ADR3 EQU $1033 ; A/D Result Register 3 ADR4 EQU $1034 ; A/D Result Register 4 BPROT EQU $1035 ; Block Protect register RESV2 EQU $1036 ; Reserved RESV3 EQU $1037 ; Reserved RESV4 EQU $1038 ; Reserved OPTION EQU $1039 ; system configuration Options COPRST EQU $103A ; Arm/Reset COP timer circuitry PPROG EQU $103B ; EEPROM Programming register HPRIO EQU $103C ; Highest Priority Interrupt and misc. INIT EQU $103D ; RAM and I/O Mapping Register TEST1 EQU $103E ; factory Test register CONFIG EQU $103F ; Configuration Control Register * Masks for serial port PORTD_WOM EQU $20 BAUD1200 EQU $B3 BAUD9600 EQU $B0 TRENA EQU $0C ; Transmit, Receive ENAble RDRF EQU $20 ; Receive Data Register Full TDRE EQU $80 ; Transmit Data Register Empty ************************************************************************* *** zero page RAM definitions ORG $00 ********************************************************************** * * * MAIN CODE * * * ********************************************************************** ORG $F800 Start: LDS #$00ff LDX #$1000 ; point to register base BSET OPTION,X %10000000 ; turn on analog subsystem BCLR SCCR2,X %00001100 * Set up SPI port LDAA #%00000110 STAA DDRD,X LDAA #%11000100 STAA SPCR,X BSET PORTD,X %00000010 LDAA SPSR,X LDAA SPDR,X *Clear the status register CLRA TAP * Insert YOUR code here MAIN BRCLR TFLG1,X %00010000 MAIN ; If 1 ms has NOT passed, continue this loop. JSR SYSTEMINT ; Otherwise, do housekeeping stuff and then BRA MAIN ; come back to this loop. ********************************************************************** * * SYSTEMINT 1 kHz system interrupt routine * * TIMER: uses TOC4 for control * * * System interrupt performs the following tasks: * * 1) Set up for next time ********************************************************************* SYSTEMINT: ************************************************************************ * setup for next (polled) interrupt ************************************************************************ LDD #2000 ; 2000 cycles = 1 millisec. ADDD TOC4,X ; add TOC4 to D STD TOC4,X ; store back BCLR TFLG1,X %11101111 ; clear OC4 for next compare RTS **************************************************************************** ********************************************************************** * This is the SPI port interupt menu code. This is the only interupt * that has been enabled. ******************************************************************** PRESPI JMP SPIDONE SPI_COM LDX #BASE ; There is a wire from TxD to digital input BRCLR SPSR,X %10000000 PRESPI ; pin 15 on the handyboard, used as busy flag. LDAB SPSR,X ;clear the flag LDAB SPDR,X BCLR SPCR,X %10000000 ;disable the interupt CASE_0 CMPB #$30 ; Do something. BNE CASE_1 ; First, see if this is what you want to do. JSR GET_C ; Get the high byte. TBA JSR GET_C ; Get the low byte. XGDY ; Put it in Y. LDAB 0,Y ; Retrieve and JSR PUT_C ; return the data. JMP SPIDONE CASE_1 CMPB #$32 ; Do something else. BNE DEFAULT ; Or don't. Make it up as you go along. JMP SPIDONE ; Etc. etc. DEFAULT INCB ; Gotta do something. JSR PUT_C SPIDONE JSR PUT_C ; Once more to say bye bye. BSET SPCR,X %10000000 ; Get the flag set. RTI **************************************************************************** * This part contains the comunication routine for the miniboard. * This routine sets the NOT BUSY bit and then waits for the master to * send a byte. Bytes are sent and received in accum. B. ***************************************************************************** GET_C PUT_C LDX #BASE STAB SPDR,X BCLR PORTD,X %00000010 BRCLR SPSR,X %10000000 * LDAB SPDR,X BSET PORTD,X %00000010 RTS ***************************************************************************** * Interrupt vectors. ***************************************************************************** * bad interrupt? return! BadInt RTI Org $FFC0 FDB BadInt ; $FFC0: Reserved FDB BadInt ; $FFC2: Reserved FDB BadInt ; $FFC4: Reserved FDB BadInt ; $FFC6: Reserved FDB BadInt ; $FFC8: Reserved FDB BadInt ; $FFCA: Reserved FDB BadInt ; $FFCC: Reserved FDB BadInt ; $FFCE: Reserved FDB BadInt ; $FFD0: Reserved FDB BadInt ; $FFD2: Reserved FDB BadInt ; $FFD4: Reserved FDB BadInt ; $FFD6: SCI Serial System FDB SPI_COM ; $FFD8: SPI Serial Transfer Complete FDB BadInt ; $FFDA: Pulse Accumulator Input Edge FDB BadInt ; $FFDC: Pulse Accumulator Overflow FDB BadInt ; $FFDE: Timer Overflow FDB BadInt ; $FFE0: Timer Input Capture 4/Output Compare 5 (TI4O5) FDB BadInt ; $FFE2: Timer Output Compare 4 (TOC4) FDB BadInt ; $FFE4: Timer Output Compare 3 (TOC3) ;BEEP; FDB BadInt ; $FFE6: Timer Output Compare 2 (TOC2) FDB BadInt ; $FFE8: Timer Output Compare 1 (TOC1) FDB BadInt ; $FFEA: Timer Input Capture 3 (TIC3) FDB BadInt ; $FFEC: Timer Input Capture 2 (TIC2) FDB BadInt ; $FFEE: Timer Input Capture 1 (TIC1) FDB BadInt ; $FFF0: Real Time Interrupt (RTI) FDB BadInt ; $FFF2: /IRQ (External Pin or Parallel I/O) (IRQ) FDB BadInt ; $FFF4: /XIRQ (Pseudo Non-Maskable Interrupt) (XIRQ) FDB BadInt ; $FFF6: Software Interrupt (SWI) FDB BadInt ; $FFF8: Illegal Opcode Trap () FDB BadInt ; $FFFA: COP Failure (Reset) () FDB BadInt ; $FFFC: COP Clock Monitor Fail (Reset) () FDB Start ; $FFFE: /RESET END ***************************************************************************